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| 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2404A-1 Zero-Delay Clock Buffer Features * * * * * * * * Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 200ps External feedback pin allows outputs to be synchronized to the clock input 5V tolerant input* Operates at 3.3V VDD Test mode allows bypass of the PLL for system testing purposes (e.g., IBIS measurements) Space-saving Packaging (Pb-free and Green Available): -- 8-pin, 150-mil SOIC (W) Description The PI6C2404A-1 is a PLL-based, zero-delay buffer, with the ability to distribute four outputs of up to 133 MHz at 3.3V. Two banks of two outputs exist, OUTA[1-2] and OUTB[1-2]. An external feedback pin is used to synchronize the outputs to the input; the relationship between loading of this signal and the other outputs determines the input-output delay. The PI6C2404A-1 is characterized for both commercial and industrial operation. * FB_IN and CLKIN must reference the same voltage thresholds for the PLL to deliver zero delay skewing Block Diagram FB_IN CLKIN PLL OUTA1 OUTA2 OUTB1 OUTB2 Pin Configuration CLKIN OUTA1 OUTA2 GND 1 2 3 4 8-Pin W 8 7 6 5 FB_IN VDD OUTB2 OUTB1 Pin Description Pin 1 2, 3 7 4 5, 6 8 C LK IN O UTA[1- 2] VDD GN D O UTB[1- 2] FB_IN Signal C lock output, Bank A 3.3V supply Ground C lock output, Bank B PLL feedback input D e s cription Input clock reference frequency (weak pull- down) 06-0036 1 PS8609A 01/13/05 CLKIN - Input to OUTA/OUTB Delay (ps) 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2404A-1 Zero-Delay Clock Buffer Zero-Delay and Skew Control CLKIN Input to Output Bank Delay vs. Difference in Loading between FB_IN pin and OUTA/OUTB pins 800 600 400 200 0 -200 -400 -600 -800 -900 Output Load Difference: FB_IN Load - OUTA/OUTB Load (pF) PI6C2404A-1 -25 -20 -15 -10 -5 0 5 10 15 20 25 -1000 The relationship between loading of the FB_IN signal and other outputs determines the input-output delay. Zero delay is achieved when all outputs, including feedback, are loaded equally. Maximum Ratings Supply Voltage to Ground Potential ............................................................................................................................. -0.5V to +7.0V DC Input Voltage (Except CLKIN) ........................................................................................................................ -0.5V to VDD +0.5V DC Input Voltage CLKIN ...................................................................................................................................................... -0.5 to 7V Storage Temperature ................................................................................................................................................... -65C to +150C Maximum Soldering Temperature (10 seconds) ........................................................................................................................... 260C Junction Temperature .................................................................................................................................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................................................... >2000V Operating Conditions (VCC = 3.3V 0.3V) Parame te r VDD TA CL CIN Supply Voltage Commerical Operating Temperature Industrial Operating Temperature Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance De s cription M in. 3.0 0 -40 M a x. 3 .6 70 85 30 15 7.3 pF Units V C 06-0036 2 PS8609A 01/25/05 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2404A-1 Zero-Delay Clock Buffer DC Electrical Characteristics for Industrial Temperature Devices Parame te r VIL VIH IIL IIH VO L VO H IDD De s cription Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Supply Current VIN = 0V VIN = VDD IO L = 8mA IO H = -8mA Unloaded outputs 100 MHz, Select inputs at VDD or GND Unloaded outputs 66 MHz, CLKIN Unloaded outputs 33MHz, CLKIN 2.4 54 39 22 mA 2.0 50 112 0.4 V A Te s t Conditions M in. M a x. 0.8 V Units AC Electrical Characteristics for Industrial Temperature Devices Parame te rs FO tDC tR tF tSK(O) N ame O utput Frequency Duty C ycle(1) Rise Time(1) Fall Time(1) O utput to O utput Skew within same bank(1) O UTA to O UTB t0 tSK(D) tJIT tLOCK Skew(1) Measured at VDD/2 Measured at VDD/2 on FB_IN pins of devices Measured at 66.67 MHz, loaded 30pF load Measured at 133 MHz, loaded 15pF load PLL Lock Time(1) Stable power supply, valid clocks presented on C LK IN and FB_IN pins 0 ps 275 500 200 150 1.0 ps ms Delay, C LK IN Rising Edge to FB_IN Rising Edge(1) Device- to- Device Skew(1) C ycle- to- C ycle Jitter(1) 30pF load 15pF load Measured at VDD/2, FOUT <66.67MHz 30pF load Measured at VDD/2, FOUT <50MHz 15pF load Measured between 0.8V and 2.0V, 30pF load Measured between 0.8V and 2.0V, 15pF load Measured between 0.8V and 2.0V, 30pF load Measured between 0.8V and 2.0V, 15pF load All outputs equally loaded 200 Te s t Conditions M in. 10 40 45 50 Typ. M ax. Units 100 133 60 55 2.2 1.5 2.2 1.5 ns MHz % Notes: 1. CLKIN and FB_IN inputs have a threshhold voltage of VDD/2. 06-0036 3 PS8609A 01/25/05 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2404A-1 Zero-Delay Clock Buffer DC Electrical Characteristics for Commercial Temperature Devices Parame te r VIL VIH IIL IIH VO L VO H IDD IDD De s cription Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Supply Current Supply Current VIN = 0V VIN = VDD IO L = 8mA IO H = -8mA Unloaded outputs 100 MHz Select Inputs @ VDD or GND Unloaded outputs, 66.67 MHz, Select inputs at VDD or GND Te s t Conditions M in. 2.0 2.4 M a x. 0.8 50 112 0.4 54 39 mA Units V A V AC Electrial Characteristics for Commercial Temperature Device Parame te rs FO tDC tR tF tSK(O) N ame O utput Frequency Duty C ycle(2) Rise Time(1) @30pF Rise Time(1) @15pF Fall Time(1) @30pF Skew(1) Fall Time(1) @15pF O utput to O utput within same bank All outputs equally loaded, VDD/2 All outputs equally loaded, VDD/2 Measured at VDD/2 Measured at VDD/2 on FB_IN pins of devices Measured at 66.67 MHz, loaded 30pF outputs Measured at 133 MHz, loaded 15pF outputs tLOCK PLL Lock Time(1) Stable power supply, valid clocks presented on C LK IN and FB_IN pins 0 Measured between 0.8V and 2.0V 30pF load 15pF load, Measured at VDD/2, FO <66.67MHz, 30pF load Measured at VDD/2, FO <50MHz, 15pF load Te s t Conditions M in. 10 40 45 50 50 Typ. M ax. Units 100 133 60 55 2.2 1.5 2.2 1.5 200 200 275 500 200 150 1.0 ms ps ns MHz % O UTA to O UTB Skew(1) t0 Input to O utput Delay, C LK IN Rising Edge to FB_IN Rising Edge(1) Device to Device Skew(1) C ycle- to- C ycle Jitter(1) tSK(D) tJIT Notes: 1. CLKIN and FB_IN inputs have a threshhold voltage of VDD/2. 2. tDC = tHIGH tHIGH + tLOW 06-0036 4 PS8609A 01/25/05 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2404A-1 Zero-Delay Clock Buffer Switching Waveforms Duty Cycle Timing VDD/2 tHIGH VDD/2 tLOW VDD/2 All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V tR 2.0V 0.8V tF 3.3V 0V Output-Output Skew OUTPUT OUTPUT VDD/2 VDD/2 tSK(O) Device-Device Skew FB_IN Device 1 FB_IN Device 2 VDD/2 VDD/2 tSK(D) Input-Output Propagation Delay INPUT FB_IN VDD/2 VDD/2 t0 Test Circuit 0.1F VDD OUTPUTS CLOAD 0.1F VDD GND GND CLK out Test Circuit for all parameters 06-0036 5 PS8609A 01/25/05 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2404A-1 Zero-Delay Clock Buffer Packaging Mechanical: 8-Pin SOIC (W) 8 .149 .157 3.78 3.99 .0099 .0196 0.25 x 45 0.50 1 .189 .196 .016 .026 0.406 0.660 REF 4.80 5.00 1.35 1.75 SEATING PLANE 0-8 .0075 .0098 0.40 .016 1.27 .050 0.19 0.25 .053 .068 .2284 .2440 5.80 6.20 .050 BSC 1.27 .013 0.330 .020 0.508 .0040 0.10 .0098 0.25 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information Orde ring Code PI6C2404A- 1W PI6C2404A- 1WE PI6C2404A- 1WI PI6C2404A- 1WIE Package Code W W W W Package De s cription 8- pin 150- mil SOIC Pb- free and Green 8- pin 150- mil SOIC 8- pin 150- mil SOIC Pb- free and Green 8- pin 150- mil SOIC Ope rating Range Commercial Commercial Industrial Industrial Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 06-0036 6 PS8609A 01/25/05 |
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